An open-source project for automated, high-performance, and easily deployable IC full-stack design.
QiMeng aims to achieve fully automated design of the chip hardware/software stack by leveraging large language models (LLMs), agents, and Boolean logic generation technologies. QiMeng has successfully automated designing RISC-V CPUs, optimizing operating system configurations, transcompiling tensor programs, and developing high-performance libraries, with performance comparable to that of human expertise.
Automatic CPU design aims to fully automated design the front-end of an entire CPU starting from I/Os.
Qimeng-cpu-v2 is the world's first CPU designed by AI, improving performance by about 380x over the state-of-the-art automated design methods, and is comparable to human-designed superscalar processors such as the ARM Cortex A53.
Qimeng-cpu-v1 is an industrial-scale RISC-V CPU design completed within 5 hours, which is over 1700× larger than the state-of-the-art automated-designed circuits. The taped-out chip is the world's first CPU designed by AI, successfully runs the Linux operating system, and performs comparably to the human-designed Intel 80486SX CPU.
Automatic HDL generation aims to train LLMs to generate HDL modules or fill the HDL code.
QiMeng-CRUX treats Verilog generation as a constrained transformation from free-form natural language to strict HDL space. We propose Core Refined Understanding eXpression (CRUX), a structured interspace to capture the essential semantics of user intent while enabling precise Verilog code synthesis. CRUX not only improves Verilog accuracy through two-stage training, but also serves as transferable, cross-model guidance that systematically enhances the stability and intent alignment of other hardware code models.
QiMeng-SALV introduces a novel framework for Verilog code generation that shifts reinforcement learning optimization from module-level to signal-level rewards. By leveraging AST analysis and signal-aware verification, it extracts functionally correct code segments from partially incorrect modules, enabling more effective RL training.
CodeV-R1 represents a further step towards accuracy by incorporating an explicit reasoning process. Before generating the final HDL code, CodeV-R1 outlines its thought process or plan, aiming to improve the logical correctness and adherence to complex requirements in the generated Verilog. CodeV-R1 exhibits test-time scaling (TTS) ability, and its 7B version is comparable to or surpasses commercial LLMs like 671B DeepSeek-R1.
CodeV is specifically fine-tuned using the described pipeline but focused primarily on the Verilog language. They are designed to generate accurate Verilog code based on natural language descriptions, achieving strong performance on Verilog-specific benchmarks. CodeV-All extends the capabilities to be multi-lingual (supporting both Verilog and Chisel) and multi-scenario.
Operating system optimization aims to automatically generate optimized operating system configurations.
AutoOS is the first framework designed to optimize the Linux kernel configurations of specific OS distributions on certain hardware without human intervention using LLMs, primarily for AIoT scenarios.
High-performance library generation aims to automatically optimize the performance of common operators (e.g., GEMM) and provides a complete automated optimization toolchain.
QiMeng-Kernel addresses the issue of excessive coupling between "optimization strategies and implementation details" in large language model (LLM)-based automatic generation of high-performance GPU Kernels by proposing a Multi-Level Macro-Micro Generation (MTMC) paradigm. Existing LLM-based methods often struggle to balance correctness and efficiency simultaneously: on one hand, the vast optimization space of GPU Kernels and their strong hardware dependence make it difficult for LLMs to search for effective strategies; on the other hand, the complexity of low-level implementation details leads to frequent compilation failures or performance degradation when directly generating complete kernel code. The proposed "Macro Thinking - Micro Coding" approach decouples high-level strategies from low-level implementations: macroscopically, it generates hardware-semantic-aware optimization decisions; microscopically, it implements these decisions through a multi-step fine-grained process, thereby maximizing correctness and improving performance. Experiments show that this method significantly outperforms existing schemes on KernelBench and TritonBench, with the correctness rate improved by over 50% and a maximum speedup of 7.3x.
Qimeng-Attention introduces a self-optimizing framework for high-performance attention code generation. By leveraging an LLM-friendly Thinking Language (LLM-TL) and a two-stage reasoning workflow, it enables LLMs to decouple optimization logic from GPU implementation. The method outperforms human-optimized libraries, achieves up to 35.16× speedup, and reduces development time from months to minutes.
QiMeng-TensorOp is an AI framework that automatically generates high-performance tensor operators with a single prompt, adapting to different hardware platforms and achieving 251% of OpenBLAS performance on RISC-V CPUs and 124% of cuBLAS on NVIDIA GPUs.
QiMeng‑GEMM presents a novel method for generating optimized implementations of the general matrix-multiplication operator (GEMM) automatically using LLMs. Based on a set of informative, adaptive, and iterative meta-prompts, it enables LLMs to comprehend the architectural characteristics of different hardware platforms and generate high performance GEMM implementations.
Compiler generation aims to leverage LLMs to complete automated compiler generation tasks.
Qimeng-NeuComBack introduces a benchmark and self-evolving framework for Neural Compilation. Leveraging the benchmark, it establishes new performance baselines of recent frontier LLMs. The proposed method enables LLMs to iteratively evolve their internal prompt strategies by extracting insights from prior self-debugging traces, thereby enhancing their neural compilation capabilities.
VEGA is an AI-driven system that simplifies compiler backend development for new targets. It abstracts existing backend functions into templates and uses a pre-trained model to auto-generate target-specific code based on target description files.
ComBack is the first public dataset designed to train language models for compiler backend development, containing 178 backends and 3 development scenarios. Models fine-tuned on ComBack significantly outperformed traditional methods, showing potential for accelerating compiler development.
Tensor program transcompiler aims to automatically perform cross-platform tensor-program conversion.
QiMeng-MuPa is an innovative mutual-supervised learning framework for automatic sequential-to-parallel code translation. It features a Translator and a Tester that co-evolve through iterative co-verify, ensuring functional equivalence and high-quality translation. QiMeng-MuPa significantly outperforms prior methods and developed the first domain-specific LLM capable of automatic code parallelization for HPC.
QiMeng-Xpiler is a neural-symbolic transcompiler that automatically translates tensor programs across heterogeneous deep learning systems such as GPUs, ASICs, and MLUs. It integrates LLMs with symbolic program synthesis to ensure both correctness and efficiency. By leveraging LLM-assisted compilation passes and hierarchical auto-tuning, QiMeng-Xpiler achieves up to 95% translation accuracy and 2× performance over vendor-optimized libraries.
BabelTower is a learning-based framework that automatically translates sequential C code into parallel CUDA code. By leveraging large-scale corpora and back-translation with discriminative reranking, it achieves up to 347× speedup and greatly improves developer productivity.
Hugging Face